Devices based on non-volatile memory cells are commonly used in several applications when the data stored therein needs to be preserved even when a power supply is off.
A largely employed solution for implementing those memory cells is based on floating-gate MOSFETs, which are typically integrated in a silicon substrate for obtaining an EPROM or an EEPROM (such as a flash memory). Typically, a floating-gate MOSFET has two gates stacked over a channel region between a source region and a drain region. The gate (referred to as floating gate) interposed between the channel region and the other gate is electrically insulated from the channel region and the other gate (for example, the floating gate is surrounded with silicon dioxide). The other gate (referred to as control gate) is electrically connected as in a common MOSFET.
Nowadays, the floating-gate MOSFETs for memory devices typically have to satisfy the existing demand for more and more compact circuits, that continually steers the microelectronics industry into submicron regions.
In particular, for allowing a more aggressive scaling of the floating gate oxide, recently some innovations for memory devices have been proposed in which gold nanoparticles are exploited as storage elements in traditional silicon devices. In detail, the floating gate is made by a layer of gold nanoparticles passivated with organic molecules over a first layer of insulating material (such as silicon dioxide) of only few nanometers. In this way, considering the length of the passivation molecules, a distance between a silicon surface and the gold nanoparticles is of only tens of nanometers. A second layer of insulating material (such as an organic insulator) overlaps the passivated nanoparticles.
In order to manufacture high-density memory devices, the control-gate, source, and drain sizes should also be reduced. However, this may impair the electric characteristics of the floating-gate MOSFET. For example, a large electric resistance can be induced or a punch-through phenomenon (in which a depletion zone of the source region contacts a depletion zone of the drain region) can occur.
Recently, memory cells implemented by exploiting carbon nanotubes have been studied. Carbon nanotubes are carbon allotropes having a structure that can be described as a sheet of graphite, rolled so as to form a cylinder and ended by two hemispheres. The carbon atoms in the nanotube are bound together so as to form hexagons. The nanotube has a nano-sized diameter and a length of the order of hundreds of nanometers; the nanotube, depending on a twist along its axis, can also feature a semiconducting electric behavior (i.e., a non-ohmic behavior affected by a control voltage).
An example of carbon nanotube memory cell is disclosed in EP1341184, which is incorporated by reference. In this case, a source electrode and a drain electrode are formed on a substrate, and a carbon nanotube is interposed between the source electrode and the drain electrode to implement a channel. A memory element is located over the carbon nanotube, and a gate electrode is formed in contact with the memory element. The memory element includes a first insulating film in contact with the carbon nanotube, a charge storage film deposited on the first insulating film, and a second insulating film formed on the charge storage film (contacting the gate electrode). Particularly, the first and the second insulating films are formed of silicon oxide, and the charge storage film is formed of silicon or silicon nitride. Alternatively, the charge storage film includes a porous film (for example, of aluminum oxide) having a plurality of nanodots filled with a charge storage material (such as silicon or silicon nitride).
A memory cell based on a vertical nanotube is instead disclosed in EP1420414, which is incorporated by reference. In detail, the memory cell includes a source region formed into a substrate; a nanotube array is composed of a plurality of nanotube columns vertically grown on the substrate (so that an end of the nanotube array is in contact with the source region). A memory element is formed around the nanotube array, and a control gate is formed around the memory element. A drain region is in contact with the other end of the nanotube array. In this solution, the memory element includes a first insulation layer formed around the nanotube array, an electron-storing layer formed around the first insulation layer, and a second insulation layer formed around the electron-storing layer (contacting the gate electrode). Particularly, the first and the second insulation layers are silicon oxide layers, and the electron-storing layer is a silicon layer, a silicon nitride layer, or a porous layer (filled with silicon or silicon nitride).
However, in the solutions known in the art, the memory element has a conventional three-layers structure. This structure may suffer from an inherent limit in its minimum thickness (for example, of the order of tens of nanometers).
In addition, the corresponding manufacturing process of the memory cells based on the nanotubes may be relatively complex and expensive. This may hinder the widespread diffusion of such a technology.